A mechanism of the PCI
standard where the target
of a data transfer is given the ability to terminate a data transfer between it and the bus master
if the target device
monopolizes the bus
due to slow access time. Access time is measured in clock cycles
, and the target will abort the data transfer once a predetermined number of clock cycles has been exceeded. The initial data transfer is allowed 16 clock cycles, and subsequent data transfers are allowed eight clock cycles. The target device will also terminate the transfer if it detects a collision
on the bus. After the transfer has been terminated, the target device will issue a retry request to the PCI bus master.