A type of memory cache
built into many modern DRAM
controller and chipset designs. Pipeline burst caches use two techniques – a burst mode
that pre-fetches memory contents before they are requested, and pipelining
so that one memory value can be accessed in the cache at the same time that another memory value is accessed in DRAM. The purpose of pipeline burst caches is to minimize wait states
so that memory can be accessed as fast a possible by the microprocessor.
The term is often abbreviated as PBC.